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August 14, 2018: GLOBALFOUNDRIES Inc. issued patent titled "Method of manufacturing selective nanostructures into finFET process flow"

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GLOBALFOUNDRIES Inc. has been issued a new U.S. patent titled "Method of manufacturing selective nanostructures into finFET process flow" by the US Patent and Trademark Office.

ABSTRACT

A method for integrating nanostructures in finFET processing and a related device are provided. Embodiments include forming fins in a Si substrate in first and second device regions; forming STI regions in spaces between fins; forming a first hardmask over the fins and STI regions; removing a portion of the first hardmask over the first device region to expose upper surfaces of the fins and STI regions in the first device region; recessing an upper portion of the fins; forming first devices over the recessed fins; forming a second hardmask over the fins and STI regions; removing a portion of the second hardmask over the second device region to expose upper surfaces of the fins and STI regions; recessing an upper portion of the fins; and forming second devices, different from the first devices, over the recessed fins, wherein the first and/or second devices include nanowire or nanosheet devices.

Appl. No.15/285,978

INDEX

SECTION 1 GLOBALFOUNDRIES INC. PROFILE

SECTION 2 PRESS RELEASES: 2018

SECTION 3 OTHER NEWS: 2018

SECTION 4 GLOBALFOUNDRIES INC. PATENTS

SECTION 5 GLOBALFOUNDRIES INC. TOP MANAGEMENT

SECTION 1 GLOBALFOUNDRIES INC. PROFILE

1.1 ACTIVITIES

GLOBALFOUNDRIES is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world's most inspired technology companies. With a global manufacturing footprint spanning three continents, GLOBALFOUNDRIES makes possible the technologies and systems that transform industries and give customers the power to shape their markets. GLOBALFOUNDRIES is owned by Mubadala Development Company.

1.2 SUMMARY

PermID: 5000707328

Website: http://www.globalfoundries.com

Industry: Semiconductors

SECTION 2 PRESS RELEASES: 2018

March 20: GLOBALFOUNDRIES Launches RF Ecosystem Program to Accelerate Time-to-Market for Wireless Connectivity, Radar and 5G Applications

GLOBALFOUNDRIES today announced a new ecosystem partner program, called RFwave(TradeMark), designed to simplify RF design and help customers reduce time-to-market for a new era of wireless devices and networks.

The last few years there has been an increasing demand for connected devices and systems that will require innovations in radio technologies to support the new modes of operation and higher capabilities. The RFwave Partner Program builds upon GF's 5G vision and roadmap, with a focus on the company's industry-leading radio frequency (RF) solutions, such as FD-SOI, RF CMOS (bulk and advanced CMOS nodes), RF SOI and silicon germanium (SiGe) technologies. The program provides a low-risk, cost-effective path for designers seeking to build highly optimized RF solutions for a range of wireless applications such as IoT across various wireless connectivity and cellular standards, standalone or transceiver integrated 5G front end modules, mmWave backhaul, automotive radar, small cell and fixed wireless and satellite broadband.

RFwave enables customers to build innovative RF solutions as well as packaging and test solutions. Initial partners have committed a set of key offerings to the program, including:

tools (EDA) that complement industry leading design flows by adding specific modules to easily leverage features of GF's RF technology platforms,

a comprehensive library of design elements (IP), including foundation IP, interfaces and complex IP to enable foundry customers to start their designs using pre-validated IP elements,

resources (design consultation, services), trained and globally distributed, for Partners to gain easy access to support in developing solutions using GF's RF technologies

Source: Company Release

SECTION 3 OTHER NEWS: 2018

July 09: GLOBALFOUNDRIES Surpasses $2 Billion in Design Win Revenue on 22FDX(Registered) Technology

GLOBALFOUNDRIES today announced that the company's 22nm FD-SOI (22FDX(Registered)) technology has delivered more than two billion dollars of client design win revenue. With more than 50 total client designs, 22FDX is proving to be the industry's leading platform for power-optimized chips across a broad range of high-growth applications such as automotive, 5G connectivity and the Internet of Things (IoT).

For clients who need significant reductions in power and die size relative to a traditional bulk CMOS process, 22FDX offers the industry's lowest operating voltage, delivering up to 500MHz frequencies at only 0.4 volts. The technology also delivers efficient single-chip integration of RF, transceiver, baseband, processor, and power management components, providing an unparalleled combination of high performance RF and mmWave functionality with low-power, high density logic for devices that require long-lasting battery life, increased processing capability, and connectivity.

"At Synaptics, as we expand upon our industry-leading mobile and PC businesses to include delivering new and innovative products that address the booming IoT market, we require the best available technologies to enable us to deliver top-notch solutions including voice and multimedia processing capabilities for our customers," said Rick Bergman, President and CEO at Synaptics.

June 28: GLOBALFOUNDRIES to Deliver Socionext's Next Generation Graphics Controller for Advanced In-Vehicle Display Applications

GLOBALFOUNDRIES today announced that Socionext Inc. will manufacture the third and latest generation of its graphics display controllers, the SC1701, on GF's 55nm Low Power Extended (55LPx) process technology with embedded non-volatile memory (SuperFlash(Registered)). The 55LPx platform enables several new features in Socionext's SC1701 series including enhanced diagnostic and security protection capabilities, cyclic redundancy code (CRC) checks, picture freeze detection, and multi window signature unit for advanced in-vehicle display systems. The shipping of the SC1701 from Socionext will start at the end of July.

In recent years, the number of in-vehicle electronic systems has risen exponentially with increasing requirements for multiple content-rich displays. Socionext's SC1701 controller integrates a variety of system component features along with APIX(Registered)3 technology and automotive safety functions to meet the increasing demand for high speed video and data connectivity and stringent safety requirements. The device supports display resolution up to one U-HD (4K) or two F-HD (2K) at 30bpp, and capable of receiving two separate video streams over a single link by utilizing the VESA(Registered) display stream compression (DSC) method.

May 29: GLOBALFOUNDRIES Enters Volume Production of Ultra High Voltage Process Technology for Industrial and Power Applications

GLOBALFOUNDRIES today announced that its 180nm Ultra High Voltage (180UHV) technology platform has entered volume production for a range of client applications, including AC-DC controllers for industrial power supplies, wireless charging, solid state and LED lighting, as well as AC adapters for consumer electronics and smartphones.

The increasing demand for highly cost-effective systems requires integrated circuits (ICs) that achieve significant area savings while reducing bill-of-materials (BOM) and printed circuit board (PCB) footprint by integrating discrete components onto the same die. GF's 180UHV platform features a 3.3V LV CMOS baseline, with options for HV18, HV30 and 700V UHV, that delivers significant area savings for both digital and analog circuit blocks, compared to the traditional 5V bipolar CMOS DMOS (BCD) technologies.

"GF's leadership in providing high voltage solutions makes the company a perfect strategic partner for On-Bright's power supply technologies," said Julian Chen, CEO of On-Bright, the leading market player in AC-DC switch mode power supply products. "GF's new 180UHV process integrates UHV components into the same IC with 180nm digital and analog by incorporating On-Bright know-how in the design.

May 23: GLOBALFOUNDRIES Announces Industry's Most Advanced Automotive-Qualified Production FD-SOI Process Technology

GLOBALFOUNDRIES today announced that its 22nm FD-SOI (22FDX(Registered)) technology platform has been certified to AEC-Q100 Grade 2 for production. As the industry's most advanced automotive-qualified FD-SOI process technology, GF's 22FDX platform includes a comprehensive set of technology and design enablement capabilities tailored to improve the performance and power efficiency of automotive integrated circuits (ICs) while maintaining adherence to strict automotive safety and quality standards.

With the rapid proliferation of automotive electronics content and regulations on energy efficiency and safety, semiconductor device component quality and reliability are more critical than ever. As a part of the AEC-Q100 certification, devices must successfully withstand reliability stress tests for an extended period of time, over a wide temperature range in order to achieve Grade 2 certification. The qualification of GF's 22FDX process exemplifies the company's commitment to providing high-performance, high-quality technology solutions for the automotive industry.

"FD-SOI has advantages for companies who are looking for real-time trade-offs in power, performance and cost," said Dan Hutcheson, CEO and Chairman of VLSI Research.

SECTION 4 GLOBALFOUNDRIES INC. PATENTS

4.1 Number of Patents Issued to GLOBALFOUNDRIES Inc. (Past 12 Months)

There were a total of 607 patents issued to GLOBALFOUNDRIES Inc. in the past 12 months. The highest number (73) were issued in October, 2017.

MonthNo. of Patents Issued
August13
July59
June36
May59
April44
March44
February50
January53
December60
November60
October73
September56
Total (Past 12 Months)607

4.2 Patents issued to GLOBALFOUNDRIES Inc. by the US PTO and the EPO on same inventions

In the past 24 months 64 patents were issued by the USPTO and the European Patent Office (EPO) to GLOBALFOUNDRIES Inc.. Recent 50 US PTO and the EPO on same inventions are as follows:

TitleUS PTOEPO
Address Based Memory Data Path Programming Scheme9,721,628; 01 Aug, 2017US9721628 (B1); 01 Aug, 2017
Chip Integration Including Vertical Field-Effect Transistors And Bipolar Junction Transistors10,002,797; 19 Jun, 2018US10002797 (B1); 19 Jun, 2018
Compensation Of Temperature Effects In Semiconductor Device Structures9,837,439; 05 Dec, 2017US9837439 (B1); 05 Dec, 2017
Connecting To Back-Plate Contacts Or Diode Junctions Through A Rmg Electrode And Resulting Devices9,548,318; 17 Jan, 2017US9548318 (B1); 17 Jan, 2017
Contact Geometry Having A Gate Silicon Length Decoupled From A Transistor Length9,412,859; 09 Aug, 2016US2016315162 (A1); 27 Oct, 2016
Contacts For A Fin-Type Field-Effect Transistor9,741,615; 22 Aug, 2017US9741615 (B1); 22 Aug, 2017
Content-Addressable Memory Having Multiple Reference Matchlines To Reduce Latency9,704,575; 11 Jul, 2017US9704575 (B1); 11 Jul, 2017
Devices And Methods For Dynamically Tunable Biasing To Backplates And Wells9,716,138; 25 Jul, 2017US9716138 (B1); 25 Jul, 2017
Dram Structure With A Single Diffusion Break10,026,740; 17 Jul, 2018US10026740 (B1); 17 Jul, 2018
Dummy Gate Used As Interconnection And Method Of Making The Same9,595,478; 14 Mar, 2017US2017141110 (A1); 18 May, 2017
Embedded Polysilicon Resistors With Crystallization Barriers9,716,136; 25 Jul, 2017US9716136 (B1); 25 Jul, 2017
Embedded Silicon Carbide Block Patterning9,922,972; 20 Mar, 2018US9922972 (B1); 20 Mar, 2018
Field Effect Transistor Structure With Recessed Interlayer Dielectric And Method10,026,818; 17 Jul, 2018US10026818 (B1); 17 Jul, 2018
Fin-Fet Resonant Body Transistor10,002,859; 19 Jun, 2018US10002859 (B1); 19 Jun, 2018
Fin-Type Metal-Semiconductor Resistors And Fabrication Methods Thereof9,595,518; 14 Mar, 2017US9595518 (B1); 14 Mar, 2017
Finfet Spacer Formation On Gate Sidewalls, Between The Channel And Source/Drain Regions9,806,078; 31 Oct, 2017US9806078 (B1); 31 Oct, 2017
Formation Of Bottom Junction In Vertical Fet Devices9,842,933; 12 Dec, 2017US9842933 (B1); 12 Dec, 2017
Integrated Circuit Structure Having Through-Silicon Via And Method Of Forming Same9,805,977; 31 Oct, 2017US9805977 (B1); 31 Oct, 2017
Integrated Circuit Structure Without Gate Contact And Method Of Forming Same9,842,927; 12 Dec, 2017US9842927 (B1); 12 Dec, 2017
Integrated Circuits With Self Aligned Contact Structures For Improved Windows And Fabrication Methods9,356,047; 31 May, 2016US2016260743 (A1); 08 Sep, 2016
Integrated Interface Structure9,875,956; 23 Jan, 2018US9875956 (B1); 23 Jan, 2018
Interconnection Cells Having Variable Width Metal Lines And Fully-Self Aligned Variable Length Continuity Cuts10,002,786; 19 Jun, 2018US10002786 (B1); 19 Jun, 2018
Interconnection Lines Having Variable Widths And Partially Self-Aligned Continuity Cuts9,887,127; 06 Feb, 2018US9887127 (B1); 06 Feb, 2018
Latency Compensation Network Using Timing Slack Sensors9,716,487; 25 Jul, 2017US9716487 (B1); 25 Jul, 2017
Metal Resistor Using Finfet-Based Replacement Gate Process9,478,625; 25 Oct, 2016US9478625 (B1); 25 Oct, 2016
Method And Process For Integration Of Tsv-Middle In 3d Ic Stacks9,553,080; 24 Jan, 2017US9553080 (B1); 24 Jan, 2017
Method And Structure For Iii-V Nanowire Tunnel Fets9,548,381; 17 Jan, 2017US9548381 (B1); 17 Jan, 2017
Method And Structure Of Forming Self-Aligned Rmg Gate For Vfet9,780,208; 03 Oct, 2017US9780208 (B1); 03 Oct, 2017
Method For Improved Fin Profile9,553,194; 24 Jan, 2017US9553194 (B1); 24 Jan, 2017
Method For Producing Self-Aligned Line End Vias And Related Device9,741,613; 22 Aug, 2017US9741613 (B1); 22 Aug, 2017
Method Including A Formation Of A Control Gate Of A Nonvolatile Memory Cell And Semiconductor Structure Including A Nonvolatile Memory Cell9,548,312; 17 Jan, 2017US9548312 (B1); 17 Jan, 2017
Method Of Concurrently Forming Source/Drain And Gate Contacts And Related Device9,837,402; 05 Dec, 2017US9837402 (B1); 05 Dec, 2017
Method Of Forming Inner Spacers On A Nano-Sheet/Wire Device9,799,748; 24 Oct, 2017US9799748 (B1); 24 Oct, 2017
Method Of Manufacturing A Semiconductor Wafer Having An Soi Configuration9,842,762; 12 Dec, 2017US9842762 (B1); 12 Dec, 2017
Method Of Using A Back-End-Of-Line Connection Structure To Distribute Current Envenly Among Multiple Tsvs In A Series For Delivery To A Top Die9,397,073; 19 Jul, 2016DE102016202738 (A1); 29 Sep, 2016
Methods For Fabricating Programmable Devices And Related Structures9,564,447; 07 Feb, 2017US9564447 (B1); 07 Feb, 2017
Methods For Forming Transistor Devices With Different Threshold Voltages And The Resulting Devices9,875,940; 23 Jan, 2018US9478538 (B1); 25 Oct, 2016
Methods For Providing Variable Feature Widths In A Self-Aligned Spacer-Mask Patterning Process9,887,135; 06 Feb, 2018US9887135 (B1); 06 Feb, 2018
Methods Of Forming Epi Semiconductor Material On The Source/Drain Regions Of A Finfet Device9,887,094; 06 Feb, 2018US9887094 (B1); 06 Feb, 2018
Methods Of Forming Fin Cut Regions By Oxidizing Fin Portions9,847,418; 19 Dec, 2017US9847418 (B1); 19 Dec, 2017
Methods Of Forming Punch Through Stop Regions On Finfet Devices On Cmos-Based Ic Products Using Doped Spacers9,508,604; 29 Nov, 2016US9508604 (B1); 29 Nov, 2016
Methods Of Forming Uniform And Pitch Independent Fin Recess9,875,939; 23 Jan, 2018US9875939 (B1); 23 Jan, 2018
Methods, Apparatus And System For Local Isolation Formation For Finfet Devices10,014,209; 03 Jul, 2018US9722053 (B1); 01 Aug, 2017
Multi-Chip Modules With Vertically Aligned Grating Couplers For Transmission Of Light Signals Between Optical Waveguides9,715,064; 25 Jul, 2017US9715064 (B1); 25 Jul, 2017
Parasitic Lateral Bipolar Transistor With Improved Ideality And Leakage Currents9,741,713; 22 Aug, 2017US9741713 (B1); 22 Aug, 2017
Sav Using Selective Saqp/Sadp9,478,462; 25 Oct, 2016US9478462 (B1); 25 Oct, 2016
Seamless Metallization Contacts9,633,946; 25 Apr, 2017US9633946 (B1); 25 Apr, 2017
Self Aligned Interconnect Structures9,922,929; 20 Mar, 2018US9922929 (B1); 20 Mar, 2018
Self-Aligned Contact Etch For Fabricating A Finfet9,905,473; 27 Feb, 2018US9905473 (B1); 27 Feb, 2018
Self-Aligned Non-Mandrel Cut Formation For Tone Inversion9,905,424; 27 Feb, 2018US9905424 (B1); 27 Feb, 2018
Self-Aligned Wrap-Around Contacts For Nanosheet Devices9,847,390; 19 Dec, 2017US9847390 (B1); 19 Dec, 2017

4.3 Previous 10 GLOBALFOUNDRIES INC. Patent titles:

Issue DateIssuing OfficePatent TitlePatent Number
Aug 14, 2018US PTOAsymmetric semiconductor device and method of forming same10,049,942
Aug 14, 2018US PTOMetal lines having etch-bias independent height10,049,926
Aug 14, 2018US PTOFDSOI channel control by implanted high-K buried oxide10,049,917
Aug 14, 2018US PTOWafer handler and methods of manufacture10,049,909
Aug 14, 2018US PTOExtrusion-resistant solder interconnect structures and methods of forming10,049,897
Aug 14, 2018US PTOControlling right-of-way for priority vehicles10,049,570
Aug 14, 2018US PTODetection of gate-to-source/drain shorts10,048,311
Aug 14, 2018US PTODirected surface functionalization on selected surface areas of topographical features with nanometer resolution10,047,431
Aug 7, 2018US PTOReliability of an electronic device10,042,969
Aug 7, 2018US PTOStructure and method for capping cobalt contacts10,043,708

4.4 Previous 5 GLOBALFOUNDRIES INC. Patent abstracts:

August 14, 2018 GLOBALFOUNDRIES Inc. issued patent titled "Asymmetric semiconductor device and method of forming same"

ABSTRACT

An aspect of the disclosure provides for an asymmetric semiconductor device. The asymmetric semiconductor device may comprise: a substrate; and a fin-shaped field effect transistor (FINFET) disposed on the substrate, the FINFET including: a set of fins disposed proximate a gate; a first epitaxial region disposed on a source region on the set of fins, the first epitaxial region having a first height; and a second epitaxial region disposed on a drain region on the set of fins, the second epitaxial region having a second height, wherein the first height is distinct from the second height.

August 14, 2018 GLOBALFOUNDRIES Inc. issued patent titled "Metal lines having etch-bias independent height"

ABSTRACT

A dielectric material stack including at least a via level dielectric material layer, at least one patterned etch stop dielectric material portion, a line level dielectric material layer, and optionally a dielectric cap layer is formed over a substrate. At least one patterned hard mask layer including a first pattern can be formed above the dielectric material stack. A second pattern is transferred through the line level dielectric material layer employing the at least one etch stop dielectric material portion as an etch stop structure. The first pattern is transferred through the line level dielectric material layer employing the at least one etch stop dielectric material portion as an etch stop structure while the second pattern is transferred through the via level dielectric material layer to form integrated line and via trenches, which are filled with a conductive material to form integrated line and via structures.

August 14, 2018 GLOBALFOUNDRIES Inc. issued patent titled "FDSOI channel control by implanted high-K buried oxide"

ABSTRACT

Methods of locally changing the BOX layer of a MOSFET device to a high-k layer to provide different Vts with one backside voltage and the resulting device are provided. Embodiments include providing a Si substrate having a BOX layer formed over the substrate and a SOI layer formed over the BOX layer; implanting a high current of dopants into at least one portion of the BOX layer; performing a high-temperature anneal of the BOX layer; forming first and second fully depleted silicon-on-insulator (FDSOI) transistors on the SOI layer, the first FDSOI transistors formed above either the BOX layer or the at least one portion of the BOX layer and the second FDSOI transistors formed above the at least one portion of the BOX layer; and applying a single voltage across a backside of the Si substrate.

August 14, 2018 GLOBALFOUNDRIES Inc. issued patent titled "Wafer handler and methods of manufacture"

ABSTRACT

A wafer handler with a removable bow compensating layer and methods of manufacture is disclosed. The method includes forming at least one layer of stressed material on a front side of a wafer handler. The method further includes forming another stressed material on a backside of the wafer handler which counter balances the at least one layer of stressed material on the front side of the wafer handler, thereby decreasing an overall bow of the wafer handler.

August 14, 2018 GLOBALFOUNDRIES Inc. issued patent titled "Extrusion-resistant solder interconnect structures and methods of forming"

ABSTRACT

Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, an interconnect structure can include: a photosensitive polyimide (PSPI) layer including a pedestal portion; a controlled collapse chip connection (C4) bump overlying the pedestal portion of the PSPI layer; a solder overlying the C4 bump and contacting a side of the C4 bump; and an underfill layer abutting the pedestal portion of the PSPI and the C4 bump, wherein the underfill layer and the solder form a first interface separated from the PSPI pedestal.

SECTION 5 GLOBALFOUNDRIES INC. TOP MANAGEMENT

Sanjay Jha, CEO

Sanjay Jha is Chief Executive Officer (CEO) of GLOBALFOUNDRIES. Appointed in January 2014, Sanjay has a successful track record of senior executive experience in the technology industry, most recently as Chairman and CEO of Motorola Mobility, which was spun out as an independent public company from Motorola Inc. in early 2011. During this period, Motorola Mobility was comprised of the Mobile Devices and Home (set-top box and cable infrastructure) businesses, as well as Motorola Mobility Ventures. He joined Motorola as co-CEO in 2008, while serving simultaneously as CEO of Motorola's Mobile Devices Business.

Prior to Motorola, Sanjay held multiple senior engineering and executive positions during his 14 years with Qualcomm, ultimately serving as Executive Vice President and Chief Operating Officer (COO) of Qualcomm Inc. from 2006 to 2008. As COO, Sanjay oversaw corporate research and development and as well as Qualcomm Flarion Technologies (QFT). Beginning in 2003 upon his appointment as President of Qualcomm CDMA Technologies (QCT), he led Qualcomm's semiconductor business and oversaw the development of five generations of modem and cell site chipsets, both digital baseband and radio frequency (RF), as well as system software. Sanjay also led the formation of Qualcomm Technologies & Ventures, where he managed both the technology investment portfolio and the new technology group as Senior Vice President and General Manager.

John Goldsberry, CFO

Dr. John Goldsberry is Chief Financial Officer for GLOBALFOUNDRIES, joining the company in 2013. He is responsible for the company's overall financial management, reporting and tax, and financial analysis functions.

John has a distinguished career in the financial world with more than 22 years of corporate finance leadership and 12 years in investment banking. Before joining GF he served as CFO for several companies, including Gateway Computers, ATS, TPI Composites, Quality Semi, DSP and The Good Guys. As an investment banker, John previously worked for Salomon Brothers and Morgan Stanley. He also is chairman of the audit committee of Sanmina.

John holds a bachelor's degree in math and a Ph.D. in finance from Harvard University

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