Private Companies 24
September 18, 2018: GLOBALFOUNDRIES Inc. issued patent titled "Wafer level electrical test for optical proximity correction and/or etch bias"
NEWS BITES - PRIVATE COMPANIES
GLOBALFOUNDRIES Inc. has been issued a new U.S. patent titled "Wafer level electrical test for optical proximity correction and/or etch bias" by the US Patent and Trademark Office. The patent number is 10,078,107 and was issued on September 18, 2018.
Three reference resistors of the same resistance and a test structure are connected in a circuit having a Wheatstone Bride design. The circuit is electrically coupled between an input and ground. A voltage applied at the input resulting in an electrical characteristic difference between two midpoints of the circuit indicates the need for corrective action with respect to a design of the test structure for either OPC or etch bias.
The invention claimed is:
1. A method, comprising: providing at least one semiconductor die; for each die, electrically connecting three reference resistors having a same designed resistance to a test structure to be tested in a circuit having a Wheatstone Bridge design, the circuit electrically coupled between an input and ground, wherein the test structure is an integrated circuit having a circuit design; testing the circuit design of the integrated circuit, wherein the testing comprises: applying a voltage across the input; and measuring for an electrical characteristic difference between two midpoints of the circuit having the Wheatstone Bridge design, the electrical characteristic difference indicating a need for one or more corrective actions to be applied to the circuit design; and applying the one or more corrective actions by modifying the circuit design to prevent the electrical characteristic difference.
2. The method of claim 1, wherein the at least one semiconductor die comprises a plurality of dies on a semiconductor wafer, and wherein the applying and measuring are performed for each of the plurality of dies.
3. The method of claim 1, wherein the electrical characteristic difference comprises a voltage difference.
4. The method of claim 1, wherein the electrical characteristic difference comprises a resistance difference.
5. The method of claim 1, wherein the reference resistors have a known optical proximity correction (OPC) bias, wherein each test structure has an unknown OPC bias, and wherein the one or more corrective actions achieves a desired resistance for the test structure.
6. The method of claim 5, wherein the at least one semiconductor die comprises at least two semiconductor dies having different test structures with different OPC biases.
7. The method of claim 1, wherein the at least one semiconductor die comprises at least two semiconductor dies having different test structures, and wherein the one or more corrective actions comprises altering an etch bias of the circuit design to substantially reduce or eliminate a difference in resistances of the different test structures.
8. The method of claim 1, wherein the one or more corrective actions correct integrated circuit design at a pre-design stage of development.
9. The method of claim 1, wherein the one or more corrective actions correct the circuit design at a design stage of development.
10. The method of claim 1, wherein the one or more corrective actions correct the circuit design at a post-design stage of development.
11. The method of claim 1, further comprising applying at least one of the one or more corrective actions to the circuit design of the integrated circuit.
To view full US patent issued to GLOBALFOUNDRIES Inc. by the US Patent Office, click here
Source: United States Patent and Trademark Office
SECTION 1 GLOBALFOUNDRIES INC. PROFILE
SECTION 2 PRESS RELEASES: 2018
SECTION 3 OTHER NEWS: 2018
SECTION 4 GLOBALFOUNDRIES INC. PATENTS
SECTION 5 GLOBALFOUNDRIES INC. TOP MANAGEMENT
SECTION 1 GLOBALFOUNDRIES INC. PROFILE
GLOBALFOUNDRIES is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world's most inspired technology companies. With a global manufacturing footprint spanning three continents, GLOBALFOUNDRIES makes possible the technologies and systems that transform industries and give customers the power to shape their markets. GLOBALFOUNDRIES is owned by Mubadala Development Company.
SECTION 2 PRESS RELEASES: 2018
March 20: GLOBALFOUNDRIES Launches RF Ecosystem Program to Accelerate Time-to-Market for Wireless Connectivity, Radar and 5G Applications
GLOBALFOUNDRIES today announced a new ecosystem partner program, called RFwave(TradeMark), designed to simplify RF design and help customers reduce time-to-market for a new era of wireless devices and networks.
The last few years there has been an increasing demand for connected devices and systems that will require innovations in radio technologies to support the new modes of operation and higher capabilities. The RFwave Partner Program builds upon GF's 5G vision and roadmap, with a focus on the company's industry-leading radio frequency (RF) solutions, such as FD-SOI, RF CMOS (bulk and advanced CMOS nodes), RF SOI and silicon germanium (SiGe) technologies. The program provides a low-risk, cost-effective path for designers seeking to build highly optimized RF solutions for a range of wireless applications such as IoT across various wireless connectivity and cellular standards, standalone or transceiver integrated 5G front end modules, mmWave backhaul, automotive radar, small cell and fixed wireless and satellite broadband.
RFwave enables customers to build innovative RF solutions as well as packaging and test solutions. Initial partners have committed a set of key offerings to the program, including:
tools (EDA) that complement industry leading design flows by adding specific modules to easily leverage features of GF's RF technology platforms,
a comprehensive library of design elements (IP), including foundation IP, interfaces and complex IP to enable foundry customers to start their designs using pre-validated IP elements,
resources (design consultation, services), trained and globally distributed, for Partners to gain easy access to support in developing solutions using GF's RF technologies
Source: Company Release
SECTION 3 OTHER NEWS: 2018
July 09: GLOBALFOUNDRIES Surpasses $2 Billion in Design Win Revenue on 22FDX(Registered) Technology
GLOBALFOUNDRIES today announced that the company's 22nm FD-SOI (22FDX(Registered)) technology has delivered more than two billion dollars of client design win revenue. With more than 50 total client designs, 22FDX is proving to be the industry's leading platform for power-optimized chips across a broad range of high-growth applications such as automotive, 5G connectivity and the Internet of Things (IoT).
For clients who need significant reductions in power and die size relative to a traditional bulk CMOS process, 22FDX offers the industry's lowest operating voltage, delivering up to 500MHz frequencies at only 0.4 volts. The technology also delivers efficient single-chip integration of RF, transceiver, baseband, processor, and power management components, providing an unparalleled combination of high performance RF and mmWave functionality with low-power, high density logic for devices that require long-lasting battery life, increased processing capability, and connectivity.
"At Synaptics, as we expand upon our industry-leading mobile and PC businesses to include delivering new and innovative products that address the booming IoT market, we require the best available technologies to enable us to deliver top-notch solutions including voice and multimedia processing capabilities for our customers," said Rick Bergman, President and CEO at Synaptics.
June 28: GLOBALFOUNDRIES to Deliver Socionext's Next Generation Graphics Controller for Advanced In-Vehicle Display Applications
GLOBALFOUNDRIES today announced that Socionext Inc. will manufacture the third and latest generation of its graphics display controllers, the SC1701, on GF's 55nm Low Power Extended (55LPx) process technology with embedded non-volatile memory (SuperFlash(Registered)). The 55LPx platform enables several new features in Socionext's SC1701 series including enhanced diagnostic and security protection capabilities, cyclic redundancy code (CRC) checks, picture freeze detection, and multi window signature unit for advanced in-vehicle display systems. The shipping of the SC1701 from Socionext will start at the end of July.
In recent years, the number of in-vehicle electronic systems has risen exponentially with increasing requirements for multiple content-rich displays. Socionext's SC1701 controller integrates a variety of system component features along with APIX(Registered)3 technology and automotive safety functions to meet the increasing demand for high speed video and data connectivity and stringent safety requirements. The device supports display resolution up to one U-HD (4K) or two F-HD (2K) at 30bpp, and capable of receiving two separate video streams over a single link by utilizing the VESA(Registered) display stream compression (DSC) method.
May 29: GLOBALFOUNDRIES Enters Volume Production of Ultra High Voltage Process Technology for Industrial and Power Applications
GLOBALFOUNDRIES today announced that its 180nm Ultra High Voltage (180UHV) technology platform has entered volume production for a range of client applications, including AC-DC controllers for industrial power supplies, wireless charging, solid state and LED lighting, as well as AC adapters for consumer electronics and smartphones.
The increasing demand for highly cost-effective systems requires integrated circuits (ICs) that achieve significant area savings while reducing bill-of-materials (BOM) and printed circuit board (PCB) footprint by integrating discrete components onto the same die. GF's 180UHV platform features a 3.3V LV CMOS baseline, with options for HV18, HV30 and 700V UHV, that delivers significant area savings for both digital and analog circuit blocks, compared to the traditional 5V bipolar CMOS DMOS (BCD) technologies.
"GF's leadership in providing high voltage solutions makes the company a perfect strategic partner for On-Bright's power supply technologies," said Julian Chen, CEO of On-Bright, the leading market player in AC-DC switch mode power supply products. "GF's new 180UHV process integrates UHV components into the same IC with 180nm digital and analog by incorporating On-Bright know-how in the design.
May 23: GLOBALFOUNDRIES Announces Industry's Most Advanced Automotive-Qualified Production FD-SOI Process Technology
GLOBALFOUNDRIES today announced that its 22nm FD-SOI (22FDX(Registered)) technology platform has been certified to AEC-Q100 Grade 2 for production. As the industry's most advanced automotive-qualified FD-SOI process technology, GF's 22FDX platform includes a comprehensive set of technology and design enablement capabilities tailored to improve the performance and power efficiency of automotive integrated circuits (ICs) while maintaining adherence to strict automotive safety and quality standards.
With the rapid proliferation of automotive electronics content and regulations on energy efficiency and safety, semiconductor device component quality and reliability are more critical than ever. As a part of the AEC-Q100 certification, devices must successfully withstand reliability stress tests for an extended period of time, over a wide temperature range in order to achieve Grade 2 certification. The qualification of GF's 22FDX process exemplifies the company's commitment to providing high-performance, high-quality technology solutions for the automotive industry.
"FD-SOI has advantages for companies who are looking for real-time trade-offs in power, performance and cost," said Dan Hutcheson, CEO and Chairman of VLSI Research.
SECTION 4 GLOBALFOUNDRIES INC. PATENTS
4.1 Number of Patents Issued to GLOBALFOUNDRIES Inc. (Past 12 Months)
There were a total of 628 patents issued to GLOBALFOUNDRIES Inc. in the past 12 months. The highest number (73) were issued in October, 2017.
|Month||No. of Patents Issued|
|Total (Past 12 Months)||628|
4.2 Patents issued to GLOBALFOUNDRIES Inc. by the US PTO and the EPO on same inventions
In the past 24 months 65 patents were issued by the USPTO and the European Patent Office (EPO) to GLOBALFOUNDRIES Inc.. Recent 50 US PTO and the EPO on same inventions are as follows:
|Address Based Memory Data Path Programming Scheme||9,721,628; 01 Aug, 2017||US9721628 (B1); 01 Aug, 2017|
|Chip Integration Including Vertical Field-Effect Transistors And Bipolar Junction Transistors||10,002,797; 19 Jun, 2018||US10002797 (B1); 19 Jun, 2018|
|Compensation Of Temperature Effects In Semiconductor Device Structures||9,837,439; 05 Dec, 2017||US9837439 (B1); 05 Dec, 2017|
|Connecting To Back-Plate Contacts Or Diode Junctions Through A Rmg Electrode And Resulting Devices||9,548,318; 17 Jan, 2017||US9548318 (B1); 17 Jan, 2017|
|Contact Geometry Having A Gate Silicon Length Decoupled From A Transistor Length||US2016315162 (A1); 27 Oct, 2016|
|Contacts For A Fin-Type Field-Effect Transistor||9,741,615; 22 Aug, 2017||US9741615 (B1); 22 Aug, 2017|
|Content-Addressable Memory Having Multiple Reference Matchlines To Reduce Latency||9,704,575; 11 Jul, 2017||US9704575 (B1); 11 Jul, 2017|
|Crack Trapping In Semiconductor Device Structures||10,068,859; 04 Sep, 2018||US10068859 (B1); 04 Sep, 2018|
|Devices And Methods For Dynamically Tunable Biasing To Backplates And Wells||9,716,138; 25 Jul, 2017||US9716138 (B1); 25 Jul, 2017|
|Dram Structure With A Single Diffusion Break||10,026,740; 17 Jul, 2018||US10026740 (B1); 17 Jul, 2018|
|Dummy Gate Used As Interconnection And Method Of Making The Same||9,595,478; 14 Mar, 2017||US2017141110 (A1); 18 May, 2017|
|Embedded Polysilicon Resistors With Crystallization Barriers||9,716,136; 25 Jul, 2017||US9716136 (B1); 25 Jul, 2017|
|Embedded Silicon Carbide Block Patterning||9,922,972; 20 Mar, 2018||US9922972 (B1); 20 Mar, 2018|
|Field Effect Transistor Structure With Recessed Interlayer Dielectric And Method||10,026,818; 17 Jul, 2018||US10026818 (B1); 17 Jul, 2018|
|Fin-Fet Resonant Body Transistor||10,002,859; 19 Jun, 2018||US10002859 (B1); 19 Jun, 2018|
|Fin-Type Metal-Semiconductor Resistors And Fabrication Methods Thereof||9,595,518; 14 Mar, 2017||US9595518 (B1); 14 Mar, 2017|
|Finfet Spacer Formation On Gate Sidewalls, Between The Channel And Source/Drain Regions||9,806,078; 31 Oct, 2017||US9806078 (B1); 31 Oct, 2017|
|Formation Of Bottom Junction In Vertical Fet Devices||9,842,933; 12 Dec, 2017||US9842933 (B1); 12 Dec, 2017|
|Integrated Circuit Structure Having Through-Silicon Via And Method Of Forming Same||9,805,977; 31 Oct, 2017||US9805977 (B1); 31 Oct, 2017|
|Integrated Circuit Structure Incorporating Non-Planar Field Effect Transistors With Different Channel Region Heights And Method||10,068,902; 04 Sep, 2018||US10068902 (B1); 04 Sep, 2018|
|Integrated Circuit Structure Without Gate Contact And Method Of Forming Same||9,842,927; 12 Dec, 2017||US9842927 (B1); 12 Dec, 2017|
|Integrated Circuits With Self Aligned Contact Structures For Improved Windows And Fabrication Methods||10,068,921; 04 Sep, 2018|
|Integrated Interface Structure||9,875,956; 23 Jan, 2018||US9875956 (B1); 23 Jan, 2018|
|Interconnection Cells Having Variable Width Metal Lines And Fully-Self Aligned Variable Length Continuity Cuts||10,002,786; 19 Jun, 2018||US10002786 (B1); 19 Jun, 2018|
|Interconnection Lines Having Variable Widths And Partially Self-Aligned Continuity Cuts||9,887,127; 06 Feb, 2018||US9887127 (B1); 06 Feb, 2018|
|Latency Compensation Network Using Timing Slack Sensors||9,716,487; 25 Jul, 2017||US9716487 (B1); 25 Jul, 2017|
|Metal Resistor Using Finfet-Based Replacement Gate Process||9,478,625; 25 Oct, 2016||US9478625 (B1); 25 Oct, 2016|
|Method And Process For Integration Of Tsv-Middle In 3d Ic Stacks||9,553,080; 24 Jan, 2017||US9553080 (B1); 24 Jan, 2017|
|Method And Structure For Iii-V Nanowire Tunnel Fets||9,548,381; 17 Jan, 2017||US9548381 (B1); 17 Jan, 2017|
|Method And Structure Of Forming Self-Aligned Rmg Gate For Vfet||9,780,208; 03 Oct, 2017||US9780208 (B1); 03 Oct, 2017|
|Method For Improved Fin Profile||9,553,194; 24 Jan, 2017||US9553194 (B1); 24 Jan, 2017|
|Method For Producing Self-Aligned Line End Vias And Related Device||9,741,613; 22 Aug, 2017||US9741613 (B1); 22 Aug, 2017|
|Method Including A Formation Of A Control Gate Of A Nonvolatile Memory Cell And Semiconductor Structure Including A Nonvolatile Memory Cell||9,548,312; 17 Jan, 2017||US9548312 (B1); 17 Jan, 2017|
|Method Of Concurrently Forming Source/Drain And Gate Contacts And Related Device||9,837,402; 05 Dec, 2017||US9837402 (B1); 05 Dec, 2017|
|Method Of Forming Inner Spacers On A Nano-Sheet/Wire Device||9,799,748; 24 Oct, 2017||US9799748 (B1); 24 Oct, 2017|
|Method Of Manufacturing A Semiconductor Wafer Having An Soi Configuration||9,842,762; 12 Dec, 2017||US9842762 (B1); 12 Dec, 2017|
|Method Of Using A Back-End-Of-Line Connection Structure To Distribute Current Envenly Among Multiple Tsvs In A Series For Delivery To A Top Die||DE102016202738 (A1); 29 Sep, 2016|
|Methods For Fabricating Programmable Devices And Related Structures||9,564,447; 07 Feb, 2017||US9564447 (B1); 07 Feb, 2017|
|Methods For Forming Transistor Devices With Different Threshold Voltages And The Resulting Devices||9,875,940; 23 Jan, 2018||US9478538 (B1); 25 Oct, 2016|
|Methods For Providing Variable Feature Widths In A Self-Aligned Spacer-Mask Patterning Process||9,887,135; 06 Feb, 2018||US9887135 (B1); 06 Feb, 2018|
|Methods Of Forming Epi Semiconductor Material On The Source/Drain Regions Of A Finfet Device||9,887,094; 06 Feb, 2018||US9887094 (B1); 06 Feb, 2018|
|Methods Of Forming Fin Cut Regions By Oxidizing Fin Portions||9,847,418; 19 Dec, 2017||US9847418 (B1); 19 Dec, 2017|
|Methods Of Forming Punch Through Stop Regions On Finfet Devices On Cmos-Based Ic Products Using Doped Spacers||9,508,604; 29 Nov, 2016||US9508604 (B1); 29 Nov, 2016|
|Methods Of Forming Uniform And Pitch Independent Fin Recess||9,875,939; 23 Jan, 2018||US9875939 (B1); 23 Jan, 2018|
|Methods, Apparatus And System For Local Isolation Formation For Finfet Devices||10,014,209; 03 Jul, 2018||US9722053 (B1); 01 Aug, 2017|
|Multi-Chip Modules With Vertically Aligned Grating Couplers For Transmission Of Light Signals Between Optical Waveguides||9,715,064; 25 Jul, 2017||US9715064 (B1); 25 Jul, 2017|
|Parasitic Lateral Bipolar Transistor With Improved Ideality And Leakage Currents||9,741,713; 22 Aug, 2017||US9741713 (B1); 22 Aug, 2017|
|Sav Using Selective Saqp/Sadp||9,478,462; 25 Oct, 2016||US9478462 (B1); 25 Oct, 2016|
|Seamless Metallization Contacts||9,633,946; 25 Apr, 2017||US9633946 (B1); 25 Apr, 2017|
|Self Aligned Interconnect Structures||9,922,929; 20 Mar, 2018||US9922929 (B1); 20 Mar, 2018|
|Self-Aligned Contact Etch For Fabricating A Finfet||9,905,473; 27 Feb, 2018||US9905473 (B1); 27 Feb, 2018|
4.3 Previous 10 GLOBALFOUNDRIES INC. Patent titles:
|Issue Date||Issuing Office||Patent Title||Patent Number|
|Sep 11, 2018||US PTO||Phase rotator apparatus||10,075,174|
|Sep 11, 2018||US PTO||Methods of forming short channel and long channel finFET devices so as to adjust threshold voltages||10,074,732|
|Sep 11, 2018||US PTO||Device with decreased pitch contact to active regions||10,074,571|
|Sep 11, 2018||US PTO||Self-aligned middle of the line (MOL) contacts||10,074,564|
|Sep 4, 2018||EPO||Vertical field effect transistor (VFET) having a self-aligned gate/gate extension structure and method||US10068987 (B1)|
|Sep 4, 2018||EPO||Integrated circuit structure incorporating non-planar field effect transistors with different channel region heights and method||US10068902 (B1)|
|Sep 4, 2018||EPO||Crack trapping in semiconductor device structures||US10068859 (B1)|
|Sep 4, 2018||US PTO||Method, apparatus and system for voltage compensation in a semiconductor wafer||10,069,490|
|Sep 4, 2018||US PTO||Method for fabricating a FinFET metallization architecture using a self-aligned contact etch||10,069,011|
|Sep 4, 2018||US PTO||Vertical field effect transistor (VFET) having a self-aligned gate/gate extension structure and method||10,068,987|
4.4 Previous 5 GLOBALFOUNDRIES INC. Patent abstracts:
September 11, 2018 GLOBALFOUNDRIES Inc. issued patent titled "Phase rotator apparatus"
A phase rotator apparatus has phase interpolation and transimpedance amplifier (TIA) stages. This separates gain and bandwidth as degrees of design freedom, facilitating a reduction in power consumption while enabling the data link to transmit and receive higher speed data. Four phases of an incoming signal are combined by the phase interpolation stage using weighting currents and current-source loads to produce a phase shifted current based signal that the TIA stage receives as input. The TIA stage then converts the signal to a voltage based signal. The quiescent operating voltage of the stage outputs can be maintained with common mode feedback circuits and injector currents.
September 11, 2018 GLOBALFOUNDRIES Inc. issued patent titled "Methods of forming short channel and long channel finFET devices so as to adjust threshold voltages"
One illustrative method disclosed herein includes, among other things, forming first and second fins for a short channel FinFET device ("SCD") and a long channel FinFET device ("LCD"), performing an oxidation process to form a sacrificial oxide material selectively on the channel portion of one of the first and second fins but not on the channel portion of the other of the first and second fins, removing the sacrificial oxide material from the fin on which it is formed so as to produce a reduced-size channel portion on that fin that is less than the initial size of the channel portion of the other non-oxidized fin, and forming first and second gate structures for the SCD and LCD devices.
September 11, 2018 GLOBALFOUNDRIES Inc. issued patent titled "Device with decreased pitch contact to active regions"
A fin cut process cuts semiconductor fins after forming sacrificial gate structures that overlie portions of the fins. Selected gate structures are removed to form openings and exposed portions of the fins within the openings are etched. An isolation dielectric layer is deposited into the openings and between end portions of the cut fins. The process enables a single sacrificial gate structure to define the spacing between two active regions on dissimilar electrical nets.
September 11, 2018 GLOBALFOUNDRIES Inc. issued patent titled "Self-aligned middle of the line (MOL) contacts"
Disclosed are methods and integrated circuit (IC) structures. The methods enable formation of a gate contact on a gate above (or close thereto) an active region of a field effect transistor (FET) and provide protection against shorts between the gate contact and metal plugs on source/drain regions and between the gate and source/drain contacts to the metal plugs. A gate with a dielectric cap and dielectric sidewall spacer is formed on a FET channel region. Metal plugs with additional dielectric caps are formed on the FET source/drain regions such that the dielectric sidewall spacer is between the gate and the metal plugs and between the dielectric cap and the additional dielectric caps. The dielectric cap, dielectric sidewall spacer and additional dielectric caps are different materials preselected to be selectively etchable, allowing for misalignment of a contact opening to the gate without risking exposure of any metal plugs and vice versa.
September 4, 2018 GLOBALFOUNDRIES Inc. issued patent titled "Vertical field effect transistor (VFET) having a self-aligned gate/gate extension structure and method"
Disclosed are embodiments of a semiconductor structure that includes a vertical field effect transistor (VFET). The VFET has a fin-shaped body that includes a semiconductor fin and an isolation fin. The semiconductor fin extends vertically between lower and upper source/drain regions. The isolation fin is adjacent to and in end-to-end alignment with the semiconductor fin. The VFET gate has a main section that wraps around an outer end and opposing sidewalls of the semiconductor fin and an extension section that extends from the main section along at least the opposing sidewalls of a lower portion the isolation fin and, optionally, around an outer end of that lower portion. A gate contact lands on the isolation fin and extends along the opposing sidewalls and, optionally, the outer end of the isolation fin down to the extension section. Also disclosed are method embodiments for forming these structures
SECTION 5 GLOBALFOUNDRIES INC. TOP MANAGEMENT
Sanjay Jha, CEO
Sanjay Jha is Chief Executive Officer (CEO) of GLOBALFOUNDRIES. Appointed in January 2014, Sanjay has a successful track record of senior executive experience in the technology industry, most recently as Chairman and CEO of Motorola Mobility, which was spun out as an independent public company from Motorola Inc. in early 2011. During this period, Motorola Mobility was comprised of the Mobile Devices and Home (set-top box and cable infrastructure) businesses, as well as Motorola Mobility Ventures. He joined Motorola as co-CEO in 2008, while serving simultaneously as CEO of Motorola's Mobile Devices Business.
Prior to Motorola, Sanjay held multiple senior engineering and executive positions during his 14 years with Qualcomm, ultimately serving as Executive Vice President and Chief Operating Officer (COO) of Qualcomm Inc. from 2006 to 2008. As COO, Sanjay oversaw corporate research and development and as well as Qualcomm Flarion Technologies (QFT). Beginning in 2003 upon his appointment as President of Qualcomm CDMA Technologies (QCT), he led Qualcomm's semiconductor business and oversaw the development of five generations of modem and cell site chipsets, both digital baseband and radio frequency (RF), as well as system software. Sanjay also led the formation of Qualcomm Technologies & Ventures, where he managed both the technology investment portfolio and the new technology group as Senior Vice President and General Manager.
John Goldsberry, CFO
Dr. John Goldsberry is Chief Financial Officer for GLOBALFOUNDRIES, joining the company in 2013. He is responsible for the company's overall financial management, reporting and tax, and financial analysis functions.
John has a distinguished career in the financial world with more than 22 years of corporate finance leadership and 12 years in investment banking. Before joining GF he served as CFO for several companies, including Gateway Computers, ATS, TPI Composites, Quality Semi, DSP and The Good Guys. As an investment banker, John previously worked for Salomon Brothers and Morgan Stanley. He also is chairman of the audit committee of Sanmina.
John holds a bachelor's degree in math and a Ph.D. in finance from Harvard University
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